1. Field of the Invention
The invention relates generally to nonvolatile memory devices, and in particular to flash memory cells and manufacturing of flash memory devices.
2. Description of Related Art
Flash memory technology includes memory cells that store charge between the channel and gate of a field effect transistor. The charge stored affects the threshold of the transistor, and the changes in threshold due to the stored charge can be sensed to indicate data.
One type of charge storage memory cell in widespread application is known as a floating gate memory cell. In a floating gate memory cell, a floating gate of conductive material, such as a conductive polysilicon, is formed over a tunnel dielectric, and an inter-poly dielectric is formed over the floating gate to isolate it from the word line or control gate of the memory cell. Although this technology has been widely successful, as the sizes of the memory cells and the distances between them shrink, the floating gate technology starts to degrade because of interference between neighboring floating gates.
Another type of memory cell, based on storing charge between the channel and gate of a field effect transistor, uses a dielectric charge trapping structure. In this type of memory cell, a dielectric charge trapping structure is formed over a tunnel dielectric which isolates the dielectric charge trapping structure from the channel, and a top dielectric layer is formed over the charge trapping structure to isolate it from the word line or gate. Representative devices are known as a silicon-oxide-nitride-oxide-silicon SONOS cells. In SONOS-type cells, the charge is stored in discrete traps, and therefore does not have a “self-leveling” characteristic like charge in floating gates. Thus, the variations across the charge trapping structure of the electric fields induced for erase and program operations, and other variations in the structures, result in non-uniform distribution of trapped charges in SONOS-type cells. The non-uniform distribution of charge results in variations in the threshold voltage across the channel.
One popular architecture for implementation of charge trapping memory devices is known as a NAND array. See, for example, FIGS. 19-21 of U.S. Patent Application Publication No. 2005/0006696A1, entitled “Semiconductor Memory,” by Noguchi et al. As explained below, NAND array-type devices exhibit non-uniform charge trapping.
Non-uniformities in the distribution of charge along the channel length direction are less problematic because the device threshold will be dominated by the local maximum threshold. However, non-uniform distribution of charge along the channel width in the dielectric charge trapping structure can result in regions along the edge of the memory cell with a lower threshold voltage, while regions toward the center of the channel have a higher threshold, or vice-versa. The different threshold regions along the sides can result in problems with program and erase characteristics and with reliability. For example, a lower threshold region along the sides of the channel can result in current flow along the sides, when the cell is intended to have a high threshold, during a process for sensing in the memory cell. As a result, the margin for sensing the states of the memory cells must be expanded to account for these variations. If the current flow on the sides of the cell is high enough, then sensing errors occur.
As the widths of the channels of memory cells decrease with advanced manufacturing technologies, and the trend for greater densities of memory cells, the problem of the non-uniform threshold due to variations in charge trapping along the sides of the channels is amplified, as it becomes a greater percentage of the overall channel width.
Recently, we proposed BE-SONOS [H. T. Lue et al, in IEDM Tech. Dig., 2005, pp. 547-550.] to solve NAND scaling problems below 30 nm nodes. Compared with the conventional SONOS, BE-SONOS uses a thin ONO tunneling barrier that allows hole tunneling during erase, while eliminating the direct tunneling leakage under the louver electric fields encountered during the periods of time in which charge retention is needed.
Therefore, it is desirable to provide a technology to address the problems with non-uniform charge concentration in the charge trapping structure along the channel width dimension.